1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method for manufacturing the same.
2. Discussion of the Related Art
A dynamic random access memory (DRAM) generally includes a cell transistor serving as a switch and a cell capacitor serving as a storage element as components. The DRAM is a volatile random access memory device, which memorizes or erases data through random access to word lines (WL) and bit lines (BL), and loses the data when the power is cut off.
On the other hand, a nonvolatile memory such as a flash memory generally includes only a transistor without a separate capacitor in each cell, different from the DRAM. Such nonvolatile memory is also known as a “floating gate” nonvolatile memory because it stores electrons in a thin gate or layer of the transistor. Non-volatile random access memory devices such as flash memory continue to store data although the power is cut off.
Flash memory can erase data in the memory cells due to a tunnel effect of electrons through a single operation, such as a flash erase operation. Further, flash memory has low power consumption and makes high-speed programming possible. Thus, flash memories may be mainly used in products in which the memory frequently changes, such as an automatic answering machine or an electronic pocket notebook.
FIG. 1 is a partial cross-sectional view of a conventional flash memory device.
With reference to FIG. 1, a general flash memory device 1 includes floating gates 20 formed on a semiconductor substrate 10 to store electric charges, control gates 40 to erase and program the electric charges stored in the floating gates 20, and a {tunnel} insulating layer 30 made of oxide-nitride-oxide (ONO) layers and formed between the floating gates 20 and the control gates 40. When the floating gates 20 are formed in cell regions, as described above, gates of high voltage transistors may be simultaneously formed in peripheral regions. Also, when the control gates 40 are formed in the cell regions, gates of low voltage transistors may be simultaneously formed in the peripheral regions.
Now, a method for manufacturing the conventional flash memory device 1, as shown in FIG. 1, will be described in brief. A field oxide layer is formed on or in the semiconductor substrate 10 made of a semiconductor material, such as silicon, and then thermal oxidation is performed, thus growing a tunnel oxide layer. Thereafter, a polysilicon layer is deposited, and then etching using photolithography is performed, thus forming the floating gates 20. In FIG. 1, the field oxide layer and the tunnel oxide layer are omitted.
Thereafter, a gate insulating layer 30 is formed by sequentially providing oxide, nitride, and oxide (ONO) layers on the floating gates 20. Next, a polysilicon layer is formed on the gate insulating layer 30, and then patterning and etching using photolithography is performed on the polysilicon-insulator-polysilicon stack, thus forming the control gate 40.
Thereafter, low concentration N-type ions and/or low concentration P-type ions are implanted into source/drain regions at sides of the floating gates 20, and spacers 50 and 60 respectively made of oxide and silicon nitride (SiN) for high concentration ion implantation into the source/drain regions are sequentially formed on the sidewalls of the gates 20 and 40. Thereafter, high concentration N-type ions and/or high concentration P-type ions are implanted using the oxide spacer 50 and the nitride spacer 60 as a mask to form junctions in the source/drain regions.
However, the nitride spacer 60, which prevents ions from being implanted into the region of the substrate 10 under the gates, may cause a physical stress on the floating gates 20. Further, when the nitride spacer 60 is formed, traps or trap sites may be formed on the semiconductor substrate 10, which may lower the reliability of the device due to deterioration during annealing.